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The hotbench.net: Web-based Interactive (on line) HDL Test-bench service for VLSI. HDL Engineers can benifit in fast development of their test-benches and test cases. HOTBENCH-system delivers the test-bench & test cases in two most widely used Hardware-Description-Languages (HDLs), viz. VHDL & Verilog.
The development of test-benches for VHDL & Verilog modules is intuitive because of the graphics-user interface.
It is intended to serve the complexity level from low to reasonably mediocre level of digital-circuits and integrated circuit designs.
In a structural VLSI design of a system, it is useful to create test-benches to verify the functionality of partitioned modules and sub-modules before subjecting the entire system design to rigorous simulation and fast verification environment.
Thus the hotbench.net is a web-based tool for developing HDL (VHDL & Verilog). It helps in substantial reduction in the time-to-market. It plays major role during initial phase of HDL modelling of design where HDL building blocks are taking shape. These building blocks later of contribute to IPs and reusable functional modules. And it is very important to test and verify these low & intermediate level modules in before instantiating into complex digital circuit (Integrated Circuits).
HDL Engineers (both Design and fast verification) can save time in following activities.
  • Determining on test-patterns/test-vectors for module that is to be subjected to fast verification.

  • Modelling the predetermined set of test-patterns/test-vectors in HDL (Verilog/VHDL).

Both of these above factors, if not carefully considered in initial phases of development cycle, may later accumulate into major man-hours crunch and result into loss of time-to-market.